The present invention relates to the formation of dielectric films, in particular to the formation of dense dielectric films in high aspect ratio features on semiconductor substrates.
It is often necessary in semiconductor processing to fill a high aspect ratio gap with insulating material. One example of a high aspect ratio trench encountered in semi-conductor processing is in the formation of shallow trench isolation (STI). As device dimensions shrink and thermal budgets are reduced, void-free filling of high aspect ratio spaces (AR>3.0:1) becomes increasingly difficult due to limitations of existing deposition processes. The deposition of doped or undoped silicon dioxide assisted by high density plasma CVD, a directional (bottom-up) CVD process, is the method currently used for high aspect ratio (AR) gap-fill. Evolving semiconductor device designs and dramatically reduced feature sizes have resulted in several applications where HDP processes are challenged in filling the high aspect ratio structures (AR>7:1) using existing technology (see, for example, U.S. Pat. No. 6,030,881). For structures representative of the 65 nm and 45 nm technology nodes, engineering the gap-fill process becomes structure dependent, hence the process needs to be reoptimized, a task of considerable complexity, every time a new structure needs to be filled.
An alternative to CVD is atomic layer deposition (ALD). ALD methods involve self-limiting adsorption of reactant gases and can provide thin, conformal dielectric films within high aspect ratio features. The ALD process involves exposing a substrate to alternating doses of, usually two, reactant gasses. As an example, if reactants A and B are first and second reactant gases for an ALD process, after A is adsorbed onto the substrate surface to form a saturated layer, B is introduced and reacts only with adsorbed B. In this manner, a very thin and conformal film can be deposited. One drawback, however, to ALD is that the deposition rates are very low. Films produced by ALD are also very thin (i.e., about one monolayer); therefore, numerous ALD cycles must be repeated to adequately fill a gap feature. These processes are unacceptably slow in some applications in the manufacturing environment.
Another more recently developed technique useful in gap fill and other dielectric deposition applications in semiconductor processing is referred to as pulsed deposition layer (PDL) processing, sometimes also referred to as rapid surface-catalyzed vapor deposition (RVD). PDL is similar to ALD in that reactant gases are introduced alternately over the substrate surface, but in PLD the first reactant A acts as a catalyst, promoting the conversion of the second reactant B to a film. In ALD the reaction between A and B is approximately stoichiometric, meaning that a monolayer of A can only react with a similar amount of B before the film-forming reaction is complete. The catalytic nature of A in PDL allows a larger amount of B to be added, resulting in a thicker film. Thus, PDL methods allow for rapid film growth similar to using CVD methods but with the film conformality of ALD methods.
Deposited oxide films often require densification in order for their properties to match those of thermally generated silicon oxide (USG), which will allow its successful integration into functioning devices. Densification removes water from the deposited film. Moreover, the conformal nature of the process results in the formation of seams in filled trenches, which may allow attack by post gap fill wet etch (HF-based) in the seam. Etching in the seam can allow for polysilicon deposition in the seam during subsequent processing which would obviate its insulating effect. Therefore, a process sequence to anneal the film and substantially eliminate seams and voids is required.
Optimally, this process sequence can operate at under 550° C., in particular under 400° C., in order to be able to meet the thermal budget requirements of advanced devices (see A. R. Londergan, et. al., J. Electrochem. Soc., vol. 148, pp. C21–C27, January 2001). In pre-metal dielectric (PMD) applications, for example, where a layer of silica is applied over gates that have been previously built-up on a substrate, there is an inherent temperature limitation due to the material used to construct the gates, usually a metal silicide such as a nickel silicide. At temperatures above about 400° C., such as in the case of conventional thermal annealing (typically conducted at temperatures in excess of 700° C.) the gate silicide may become discontinuous, thereby increasing the resistance of the circuit and leading to performance problems. Further, there may be two or three PMD layers in a given device. Thus, it is desirable to implement a method to improve the material properties of the dielectric film and, for example, eliminate seams or voids in filled gaps, ideally maintaining temperatures that are low enough to avoid damaging underlying heat sensitive structures.